`default_nettype none

//<<<<<<< local
//module Decoder ( clk, mult, pattern, rd_en, dout,cnt_out);
//=======
module Decoder ( clk, reset, mult, pattern, rd_en, dout, cnt_out,reset_value);
//>>>>>>> other

parameter mult_width = 32;
parameter pattern_width = 32;

input wire 						clk;
input wire 						reset;
input wire [mult_width-1:0] 	mult;
input wire [pattern_width-1:0] 	pattern;
output wire						rd_en;
output reg [pattern_width-1:0]	dout;
output wire	[mult_width-1:0]	cnt_out;
input wire [3:0]				reset_value;

reg [mult_width-1:0]			count;


assign cnt_out=count;


assign rd_en = (count == 0) ? 1 : 0;

always @(posedge clk) begin

	if ( reset ) begin
	    count <= 1;
	    dout <= {
			reset_value[3], reset_value[3],reset_value[3], reset_value[3],reset_value[3],reset_value[3], reset_value[3],reset_value[3],
			reset_value[2], reset_value[2],reset_value[2], reset_value[2],reset_value[2],reset_value[2], reset_value[2],reset_value[2],
			reset_value[1], reset_value[1],reset_value[1], reset_value[1],reset_value[1],reset_value[1], reset_value[1],reset_value[1],
			reset_value[0], reset_value[0],reset_value[0], reset_value[0],reset_value[0],reset_value[0], reset_value[0],reset_value[0]
			};
	end else begin
		if ( count == 0 ) begin
		    dout <= pattern;
	    	count <= mult;
		end else begin
		    count <= count - 1;	    
		end    
	end

end

endmodule
